Data Authenticator for the Deployable Seismic Verification System

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### APPENDIX Q

### NSS Authenticator Addresses

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                        NSS AUTHENTICATOR ADDRESSES

      Addresses are jumper selectable and given in Hex.  Blank entries
      in the table indicate unused ports.  Addresses refer to ports on
      the internal bus.

      External Bus Exerciser

      The most significant (high order) bit is 7 while the least
      significant (low order) is 0.  Osc refers to the hardware
      sequencer of the D, V, F and R registers.  Osc resides on the V
      register card.

                Read                           Write

      FF00      Authenticator status           D register
                D register offline   bit 7
                Watchdog time out    bit 6
                Data out ready       bit 5
                Software busy        bit 4
                Poll microcontroller bit 3
                INT1 status          bit 2
                INT0 status          bit 1
                Osc busy             bit 0
      FF01
      FF02      Low byte R register
      FF03      High byte R register
      FF04      Clear R register
      FF05      Data in                        Data out
      FF06                                     Frame start
      FF07

                Read                           Write

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      FF08      Reset                          Clear Reset
      FF09      OUT1 and OUT2                  not used
      FF0A
      FF0B
      FF0C
      FF0D
      FF0E

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      Bus Decode/Bus View

      Axx and Bxx refer to sides (A and B) and pin numbers (1-31) of
      the IBM XT compatible 31/2 edge connector.  Px.x refers to 8051
      microcontroller port pins.  The most significant (high order) bit
      is 7 while the least significant (low order) is 0.

                Read                          Write

      FFB0      0        bit 7
                0        bit 6
                0        bit 5
                0        bit 4
                0        bit 3
               -ROM B27 bit 2
               -RAM B26 bit 1
                B24     bit 0

      FFB1      B23      bit 7
                B22      bit 6
                B21      bit 5
                B18      bit 4
                B17      bit 3
                B16      bit 2
                B15      bit 1
                B6       bit 0

      FFB2      B3         bit 7
                Bl         bit 6
                P3.5 Tl    bit 5
                P3.4 TO    bit 4
                P3.3 -INT1 bit 3
                P3.2 -INT0 bit 2
                P3.1 TxD   bit 1
                P3.0 RxD   bit 0

      FFB3      P1.7 Bl9 bit 7
                P1.6 B10 bit 6
                P1.5 A15 bit 5
                P1.4 B8  bit 4
                P1.3 A14 bit 3
                P1.2 A13 bit 2
                P1.1 B5  bit 1
                P1.0 A12 bit 0

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      Command/Status Register

      Osc refers to the hardware sequencer of the D, V, F and R
      registers.  Osc Clk & D means that the hardware sequencer is
      supplying clock and data to the D, V, F, and R registers opposed
      to the authenticator providing clock and data to these registers
      via port pins P3.1 and P3.0 respectively.

                Read                          Write

      FFAO      Data in                       Data out
      FFA1
      FFA2      Status
                D register offline   bit 7
                Watchdog time out    bit 6
                Data out ready       bit 5
                Software busy        bit 4
                Poll microcontroller bit 3
                INT1 status          bit 2
                INT0 status          bit 1
                Osc busy             bit 0
      FFA3                                    Ext Clk & D
      FFA4                                    Int Clk & D
      FFA5
      FFA6
      FFA7

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      V Register

      XTAL Clk & D refers to the CMOS crystal oscillator providing the
      clock to the D, V, F, and R state sequencer.  P3.1 Clk & Data
      refers to Port 3.1 providing a software clock to the sequencer.
      Software GO initiates a cycle of the sequencer from software.  In
      operational mode GO is initiated by a write the the D register.
      FR count is the number of positive edge clock pulses received by
      the F and R registers.

                Read                          Write

      FFD0      Low byte V register
      FFDl      High byte V register
      FFD2                                    Int Clk & D
      FFD3                                    Ext Clk & D
      FFD4                                    Software GO
      FFD5      P3.1 Ext Clk & D
      FFD6      XTAL Int Clk & D
      FFD7      FR count                      FR count

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      F Register

      The F register is a 63 bit linear feedback shift register.   It
      is implemented in hardware with eight 8 bit shift registers
      designated FO through F7.  FO contains the least significant bits
      while F7 the most.  The 64th bit, bit 0 of Fo, is unused.

                Read                          Write

      FFEO      F0 bit 0 unused               Clear F
      FFEl      Fl                            Int Clk & D
      FFE2      F2                            Ext Clk & D
      FFE3      F3
      FFE4      F4
      FFE5      F5
      FFE6      F6
      FFE7      F7

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      R Register

      The R register is a 14 bit nonlinear feedback shift register.
      It is implemented in hardware with two 8 bit shift registers
      designated RO and Rl. RO contains the least significant bits
      while Rl the most.  Bit 1 of R0 is unused and is grounded.  The
      feedback function is controlled by the contents of a fast 16Kx1
      RAM.  Bit 0 of R1 is used to read the output, Q, of the fast RAM
      when BUSY is asserted.  The fast RAM is in a low power when BUSY
      is not asserted.

                Read                          Write

      FFCO      R0 bit 1 unused, bit 0 Q
      FFCl      Rl
      FFC2                                    Clear R
      FFC3
      FFC4                                    Int Clk & D
      FFC5                                    Ext Clk & D
      FFC6
      FFC7

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      Watchdog Timer

                Read                          Write

      FF60      Watchdog value                Clear watchdog
      FF61      Enable watchdog output        Disable watchdog output
      FF62      Enable watchdog osc           Disable watchdog osc
      FF63

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      Clock/Calendar

      The clock/calendar is a Harris/GE/Intersil/RCA ICM 7170 uP-
      Compatible Real-Time Clock.  Details of it addressing the
      functions are given in publication 301680-007 August 1987.

                Read                          Write

      FF80      Counter-l/100 sec             Counter-1/100 sec
      FF81      Counter-hours                 Counter-hours
      FF82      Counter-minutes               Counter-minutes
      FF83      Counter-seconds               Counter-seconds
      FF84      Counter-month                 Counter-month
      FF85      Counter-date                  Counter-date
      FF86      Counter-year                  Counter-year
      FF87      Counter-day of week           Counter-day of week
      FF88      RAM-l/100 sec                 RAM-1/100 sec
      FF89      RAM-hours                     RAM-hours
      FF8A      RAM-minutes                   RAM-minutes
      FF8B      RAM-seconds                   RAM-seconds
      FF8C      RAM-month                     RAM-month
      FF8D      RAM-date                      RAM-date
      FF8E      RAM-year                      RAM-year
      FF8F      RAM-day of week               RAM-day of week
      FF90      Interrupt status              Interrupt mask
      FF91                                    Command register

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      Buzzer and LEDs

      The piezoelectric buzzer is operated from two port pins
      controlled by software.

                Read                          Write

      FF70      buzzer 0 bit 0                buzzer 0 bit 0
                buzzer 1 bit 1                buzzer 1 bit 1
                LED 1    bit 2                LED 1    bit 2
                LED 2    bit 3                LED 2    bit 3
                LED 3    bit 4                LED 3    bit 4
                LED 4    bit 5                LED 4    bit 5
                LED 5    bit 6                LED 5    bit 6
                LED 6    bit 7                LED 6    bit 7

      FF71

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      EEPROM key memory

                Read                          Write

      FF50      data byte                     data byte
      FF51                                    Address low byte
      FF52                                    Address high byte
      FF53     -OE+5  bit 0                  -OE+5  bit 0
               -OE+12 bit 1                  -OE+12 bit 1
                A9+12 bit 2                   A9+12 bit 2
               -WE+12 bit 3                  -WE+12 bit 3
               -CE    bit 4                  -CE    bit 4
                      bit 5                         bit 5
                      bit 6                         bit 6
               +12 on bit 7                  +12 on bit 7

      FF54
      FF55
      FF56
      FF57

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      Maintenance 8upport Board

      The maintenance support board contains a National 90C52
      asynchronous communications element and a 32Kx8 CMOS EPROM or
      EEPROM.

                Read                          Write

      FFF0      Receiver buffer               Transmitter buffer
      FFFl      Interrupt enable              Interrupt enable
      FFF2      Interrupt identification
      FFF3      Line control                  Line control
      FFF4      MODEM control                 MODEM control
      FFF5      Line status                   Line status
      FFF6      MODEM status                  MODEM status